In recent years, a synchronous memory that performs in synchronization with a clock signal has been widely used as a main memory for a personal computer and the like. In particular, in a synchronous memory of a DDR (Double Data Rate) type among various types of synchronous memories, a DLL circuit that generates an internal clock signal synchronized with an external clock signal is essential because it is necessary to synchronize input/output data with the external clock signal precisely.
Patent Document 1 discloses a DLL circuit including: initial delay monitoring means that generates an initial setting code according to a phase difference between a reference clock signal and a feedback clock signal at an operation start time point; a shift register that generates a delay control code in response to the initial setting code; and a delay line that delays the reference clock signal in response to the delay control code. According to the DLL circuit mentioned above, such an effect is obtained that the DLL circuit has a fast locking time by monitoring the phase of the feedback clock signal at the time of initial operation and setting the delay control code based on the result of the monitoring operation.
Patent Document 2 disclosed a DLL circuit comprising: a phase determination circuit that generates a phase determination signal based on a phase of a first clock signal; a first counter circuit that updates a count value in each sampling period based on the phase determination signal; a first delay line that generates a second clock signal by delaying the first clock signal based on the count value; and a first invalidation circuit that invalidates a change of the phase determination signal within the same sampling period in response to a fact that the phase determination signal indicates a first logical level. According to the DLL circuit described above, in a case where a determination signal varies within a sampling period, the determination signal is held to a predetermined logical level by the invalidation circuit, which makes it possible to exclude a component that affects the determination signal in a short period, such as a noise or jitter component.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P2009-141954A, which corresponds to U.S. Pat. No. 7,737,746B2    [Patent Document 2]    JP Patent Kokai Publication No. JP-P2010-187229A, which corresponds to US2010/201413A1